Designing Chip-Level Nanophotonic Interconnection Networks
نویسندگان
چکیده
منابع مشابه
Nanophotonic On-Chip Interconnection Networks for Energy-Performance Optimized Computing
1. Introduction Much recent progress in silicon nanophotonic technology has enabled the prospect of high-performance nano-photonic networks-on-chip (NoCs), which have become very attractive solutions to the growing bandwidth and power consumption challenges of future high-performance chip multiprocessors [1–4]. The design of our high-performance nanophotonic NoC commences at the individual sili...
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My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels. As chips grow increasing larger and faster, power and design-time requirements become more aggressive, and timing variabilit...
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......VLSI technology’s increased capability is yielding a more powerful, more capable, and more flexible computing system on single processor die. The microprocessor industry is moving from singlecore to multicore and eventually to manycore architectures, containing tens to hundreds of identical cores arranged as chip multiprocessors (CMPs). Another equally important direction is toward system...
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This paper considers various physical constraints which influence the design of interconnection networks used in multiprocessor systems. Design expressions are presented for implementing an N log N packet passing interconnection network composed for circuit switched crossbar chip modules. Expressions reflecting chip level and board level pin and area constraints are derived and used to determin...
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The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of s...
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ژورنال
عنوان ژورنال: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
سال: 2012
ISSN: 2156-3357,2156-3365
DOI: 10.1109/jetcas.2012.2193932